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Lu Nianduan, Wang Lingfei, Li Ling, Liu Ming. A review for compact model of graphene field-effect transistors . Chinese Physics B, 2017, 26(3): 036804  
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A review for compact model of graphene field-effect transistors
Lu Nianduan 1 , 2 , 3 , Wang Lingfei 1 , 3 , Li Ling 1 , 2 , 3 , †, Liu Ming 1 , 2 , 3
Key Laboratory of Microelectronic Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
University of Chinese Academy of Sciences, Beijing 100049, China
Jiangsu National Synergetic Innovation Center for Advanced Materials (SICAM), Nanjing 210009, China

 

† Corresponding author. E-mail: lingli@ime.ac.cn

Abstract

Graphene has attracted enormous interests due to its unique physical, mechanical, and electrical properties. Specially, graphene-based field-effect transistors (FETs) have evolved rapidly and are now considered as an option for conventional silicon devices. As a critical step in the design cycle of modern IC products, compact model refers to the development of models for integrated semiconductor devices for use in circuit simulations. The purpose of this review is to provide a theoretical description of current compact model of graphene field-effect transistors. Special attention is devoted to the charge sheet model, drift-diffusion model, Boltzmann equation, density of states (DOS), and surface-potential-based compact model. Finally, an outlook of this field is briefly discussed.

PACS: 68.35.bg;72.80.Vp
Keyword:two-dimensional material;graphene;field-effect transistor;compact model
1. Introduction

As a two-dimensional material with honeycomb structure, graphene has attracted enormous interests because of its unique properties since its debut in 2004.[1–3] Its unique physical, mechanical, and electrical properties have drawn a lot of interests among scientists.[4–6] Graphene not only exhibits excellent optoelectronic and mechanical properties but also can provide good adhesion with several organic materials so as to produce high-performance organic field-effect transistors.[7–10] Compared with conventional semiconductors, such as silicon, graphene shows completely different properties, for example, it is a zero-overlap semiconductor with very high electrical conductivity, and its conduction and valence bands meet at the Dirac point. For semiconductors, the flow of electricity requires some kinds of activation (such as heat or light absorption) to get over the gap between the valence band and conduction band. If the semiconductor is activated by an external electric field to switch on and off, then it is called field-effect transistors (FETs).[11,12] A FET consists of a gate, a channel region connecting source and drain electrodes, and a barrier separating the gate from the channel, as shown in Fig. 1(a). The operation of a conventional FET relies on the control of the channel conductivity, and thus the drain current, by a voltage applied between the gate and the source. The corresponding transfer characteristics curve of FET is shown in Fig. 1(c). Generally speaking, the large-scale and bilayer graphene does not possess a band gap. However, constraining large-scale graphene in one dimension or applying an electric field perpendicularly on the bilayer graphene can induce a band gap.[13–15] Recently, both theoretical and experimental works have achieved the graphene FETs.[16–18] Figure 1(b) shows a structure of top-gated graphene FET (GFET). The corresponding transfer characteristics curve for two GFETs with large-area-graphene channel is shown in Fig. 1(d). One can see in Fig. 1 that, due to the structure different between conventional MOSFET and GFET, the transfer characteristics curve shows entirely different features. For example, the transfer characteristics curves of GFETs have two kinds of conductions, i.e., hole conduction and electron conduction, while MOSFET has a unique current–voltage transfer characteristic.

Fig. 1. (color online) Cross-section of (a) a n-channel MOSFET and (b) a top-gated graphene FET, (c) MOSFET transfer characteristics showing (on a logarithmic scale on the left and a linear scale on the right) versus the gate-source voltage ( ), and (d) transfer characteristics curves for two GFETs with large-area-graphene channel.[11]

Semiconductor device model, being a connection bridge between semiconductor manufactures and circuit designers, plays a critical role in semiconductor industry.[19,20] With the development of CMOS technology, which brings plenty of new physical effects, semiconductor device model has rapidly developed. Currently, integrated circuit (IC) designers use various kinds of software (such as SPICE, SLIC, PHILIPAC) in circuit design.[21–23] The core of the corresponding software is the model of each unit device. Because an integrated circuit includes plenty of transistors, if all unit devices use the complicated model of transistor, the system level simulation will beyond computer ability and hence results in non-convergence in calculation. On the other hand, the transistor model can accurately describe its physical properties in order to ensure the reliability of the calculated result.

It is reasonable to state what a compact model is, since one may see differences in interpretations in the past. The following requirements for an excellent compact model have been considered in Refs. [24] and [25].

Compact model is a critical step in the design cycle of modern IC products.[26] It refers to the development of models for integrated semiconductor devices for use in circuit simulations. The models are used to reproduce device terminal behaviors with accuracy, computational efficiency, ease of parameter extraction, and relative model simplicity for a circuit or system-level simulation, for future technology nodes.[27] Physics-based models are often preferred, particularly when concerned with statistical or predictive simulation. The industry’s dependence on accurate and time-efficient compact models continues to grow as circuit operating frequencies increase and device tolerances scale down with concomitant increases in chip device count, and analog content in mixed-signal circuits. Accurate and physics-based compact models are useful for the design and development of FETs for digital and analog circuits. These models are highly desirable because they offer better computational efficiency than their numerical alternatives without loss of physical insights. Since Kacprzak et al. reported firstly the compact DC model of GaAs-FETs in 1983,[28] the compact model for FETs has received much attention.[29–33] Figure 2 shows the Thomson Reuters Web of Science publication report for the topic “Compact Model for Field-Effect Transistors” in the last 20 years and “Compact Model for Graphene FET”. Research interest in the compact model has been growing remarkably over the last 10 years. The earliest compact model for graphene FET was reported by Meric et al. in 2008,[34,35] which is based on the charge sheet model of MOSFET. Following Meric’s model, several evolving compact models have been established,[36–39] such as, virtual-source current–voltage model, SPICE-compatible compact model, and electrical compact model, etc. With the decrease of channel lengths to below 50 nm, traditional compact models lose validity. To satisfy the scale-down requests, the quasi ballistic FET model has been developed for nano scale FETs.[40] However, due to the difference of structure and transport feature between MOSFET and GFETs, the model of MOSFET maybe not entirely practicable to GFETs. Some new compact models, for example, based on a drift-diffusion model[41–45] and Boltzman equation,[46] have also been developed. Further, some new physical-based compact models, such as surface-potential-based[47,48] and based on density of states (DOS),[49–51] have been developed to achieve high accuracy and more physical.

Fig. 2. (color online) Thomson Reuters Web of Science publication report for the topic, (a) “Compact Model for Field-Effect Transistors” in the last 20 years, and (b) “Compact Model for Graphene FET”.

There have been some excellent reviews published recently with emphasis on the basic science of graphene and graphene FETs.[7,11,52–57] Given the growing interest in graphene in the electron-device community, and ongoing discussions of the potential of graphene transistors, a review article focusing on compact model of graphene FETs is timely. In this review, we mainly focus on the compact model of graphene FETs based on different methods, including not only based on conventional MOSFET model but also new physical-based model. In Section 2, the theoretical basis of compact model is discussed. In Sections 3–7, the charge sheet model, drift-diffusion model, Boltzmann equation, surface-potential-based compact model and the model based on density of states (DOS) are summarized. Finally, the future outlook for this field is briefly discussed in Section 8.

2. Theoretical basis of compact model

As mentioned above, the first compact model for FETs was proposed by Kacprzak et al. in 1983.[28] After more than 30 years, several researchers have developed various compact models for FETs. All these proposed compact models can be divided into two categories, one is charge-based and the other is surface-potential-based. Next, we will describe the theoretical basis of compact models developed from charge-based and surface-potential-based, respectively.

2.1. Charge sheet model

The charge sheet model is applied to long-channel devices. As compared with other models, such as Pao-Sah model,[58] the charge sheet model leads to a very simple algebraic formula for the current of long-channel devices, which can be used in all regimes from subthreshold to saturation. The charge sheet model firstly assumes a quasi-Fermi level formulation for carrier densities and the coordinate system. The source-to-drain current I can be related to the average quasi-Fermi level gradient and the carrier density per unit area N(y)[59]

(1)
where Z is the channel width, μ is the effective mobility, q is the elementary charge, and y is the measured distance along the channel from the source toward the drain, . is the minority carrier density per unit volume in excess of the zero band-banding density . can be simply approximated by
(2)
where is the potential along the oxide–silicon interface and . By integrating Eq. (2), one can obtain
(3)
That is, equation (2) is equivalent to the assumption that the carrier density along the channel varies only because the inversion layer moves rigidly with respect to the quasi-Fermi level as the potential varies. All shape dependence of the inversion layer upon carrier density or normal field is contained in and remains unaltered from source to drain.

By substituting Eq. (2) into Eq. (1), one can solve Eq. (1) for to obtain

(4)
The model is then addressed by using Poisson’s equation for the potential
(5)
where one can assume p-type material. Equation (5) is joined across the oxide–silicon interface by the discontinuity condition
(6)
where refers to evaluation on the oxide side of the interface, on the silicon side. The x-coordinate measures the normal distance from the interface to the silicon. Equation (6) implies that N(y) is contained in a charge sheet of zero thickness. This in turn means that (i) the current is constrained to flow along the oxide–silicon interface, and (ii) there is no voltage drop across the inversion layer. Using some arbitrary , one can solve Eq. (5) for Φ in both oxide and semiconductor. This determines the normal derivatives in Eq. (6). Using Eq. (4), one can obtain an integral equation for . This equation now will be set up and solved for long channel devices.

2.2. Boltzmann equation

In order to model the transport characteristics of the GFET, one can split carrier distribution function into its even and odd parts, that is, . Then, it is well known that in the presence of randomizing collisions, and even in high fields, the Boltzmann transport equation can be written as[46,60]

(7)
with and the i-index indicates a particular scattering mechanism. In the presence of strong inter-carrier scattering for high carrier concentration, the even part of the distribution is thermalized at an electronic temperature , and reads as
(8)
where defines the carrier concentration along the channel. In p-channel, the current can be calculated as
(9)
where L is the channel length, and the factor 4 accounts for the spin and the two-fold degeneracy of the Dirac point. Here, and θ is the angle between the electric field and the vector k. Then for , one can approximate by a delta function centered around . After integrating and setting ,[61] the hole current in a 2D graphene layer reads
(10)
where W is the graphene layer width, p is the hole concentration, F is the electric field, and τ(p) is the relaxation time (inverse scattering rate) for a particular carrier concentration p. In the high field regime, one can assume , where is the critical electric field for the onset of high energy collisions such as remote phonons,[62] for instance, is the low-field relaxation time dominated by scattering with charged impurities with density , and is a time constant. By setting , one recovers the conventional current expression
(11)
with , where the low-field conductance , as observed experimentally.[61]

2.3. Drift-diffusion carrier transport

In semiconductor physics, the drift-diffusion equation is related to drift current and drift velocity. The equation at the steady state for electrons and holes, respectively, is normally written as[20,63]

(12)
(13)
where n and p are the concentrations (densities) of electrons and holes, respectively, and are the electric currents due to electrons and holes, respectively, and are the corresponding “particle currents” of electrons and holes, respectively, R represents carrier generation and recombination, E is the electric field vector, and and are electron and hole mobilities, respectively.

The diffusion coefficient and mobility are related by the Einstein relation[64]

(14)
The drift and diffusion currents refer separately to the two terms in the expressions for J
(15)
where μ is the mobility of electrons (holes)

2.4. Density of states (DOS)

The density of states for monolayer graphene is expressed as[65]

(16)
And the Fermi level varies linearly with the voltage drop (i.e. ) across the quantum capacitance , which implies that .

The DOS for bilayer graphene can be written as[66]

(17)
where is the effective mass, is the bilayer energy bandgap, is the reduced Planck constant, H is the Heaviside step function, and A is a fitting parameter.

2.5. Surface potential

Surface potential , i.e., the potential at the interface is an implicit function of the terminal voltages that is usually obtained by solving the surface potential equation (SPE) occasionally known also as the input voltage equation.[67] It is derived under several simplifying assumptions essential in the compact model formulation. The first simplification is the Shockley’s gradual channel approximation (GCA) that assumes

(18)
where ϕ denotes the electrostatic potential. With this simplification, the Poisson equation becomes
(19)
where ρ denotes the charge density and is the dielectric permittivity. By denoting the electron and hole concentrations as n and p respectively,
(20)
where is the concentration of ionized acceptors and one can consider an n-channel MOS device. Since the hole current component is negligible, it is the gradient of the hole imref and the hole concentration is given by the Boltzmann relation where and denotes the thermal potential. This form assumes that the reference point for the potential is in the neutral bulk region, where the majority and minority carrier concentrations are and respectively. For electrons, it is necessary to take into account the imref gradient so that
(21)
where the normalized imref splitting (a.k.a.“channel voltage”)
(22)

For most applications, it is sufficient to assume the complete ionization of the channel dopants. Then coincides with the total acceptor concentration (for the uniformly doped channel). Hence

(23)
where .

From Eq. (19) and the boundary condition for φ = 0, it follows that

(24)
where the surface electric field . Continuity of the normal component of the displacement vector at the Si/ interface provides SPE in the form
(25)
where is the flat-band voltage, denotes the body factor, unit area oxide capacitance , is the oxide thickness, and is the oxide permittivity. The dimensionless variable h represents the normalized square of the surface electric field
(26)

3. Charge sheet compact model

The first compact model for GFET was proposed by Meric et al. based on charge sheet model.[34,35] In Meric’s model, it is assumed that a top-gated graphene FET is based on a high- k gate dielectric without bandgap engineering. And the GFETs have source and drain regions that are electrostatically doped by the back gate, which enables control over the contact resistance and threshold voltage of the top-gated channel. Then, the sheet carrier concentrations (electrons or holes) in the source and drain regions are given as

(27)
where and are the back-gate-to-source voltage and back gate voltage at the Dirac point in these regions, respectively, and n is the minimum sheet carrier concentration as determined by disorder and thermal excitation. is the back-gate capacitance Under the top gate, the carrier concentrations are determined by both the front and back gates
(28)
where , which has the character of a threshold voltage, is given by
is the top-gate-to-source voltage, is the top-gate capacitance and given by the parallel combination of the electrostatic capacitance of the gate and the quantum capacitance of graphene.

Then, the carrier concentration dependence of the distance in the channel, shown schematically in Fig. 3 for different points in the I–V trace, is calculated using a field-effect model

(29)
With this consideration, the current in the channel is express by[68]
(30)
where L is the channel length and W is the channel width. Current continuity forces a self-consistent solution for the potential V(x) along the channel. Here the carrier drift velocity ( ) is approximated by a velocity saturation model[69]
(31)
where is the saturation velocity of the carriers.

Fig. 3. (color online) (a) Measured I–V characteristic at V and V in GFET devices. Three points (I, II, and III) are indentified in the I–V curve. (b) Schematic demonstration of the carrier concentration under the top-gated region. At point I ( , , here means the of “kink” between I and II, or II and III in panel (a)), the channel charge at the drain end begins to decrease as the minimal density point enters the channel. At point II ( ), the minimal density point forms at the drain. For (point III), an electron channel forms at the drain.[35]

By combining Eqs. (29)–(31), the final current in the channel can be obtained as

(32)

Figure 4 shows the results of simple field-effect modeling of the devices, compared with the measured I–V characteristics of GFET. This field-effect model is also implemented in Verilog-A with the equations. Here, is approximately 100 Ω (700 Ω) for two kinds of GFET devices, i.e., GFET A and GFET B. GFET A has a low-field mobility cm /V⋅s and cm , compared with cm /V⋅s and cm for GFET B.

Fig. 4. (color online) Current–voltage characteristics of GFET device. Drain current as a function of source-to-drain voltage (a) for GFET A at V, −0.3 V, −0.5 V and (b) for GFET B at V, −0.5 V, −1.5 V, −2.5 V (from bottom to top), respectively. Both measured (solid curves) and simulated (dashed curves) results are shown. Inset is the equivalent circuit for the corresponding compact model of GFET.[34]

Based on the Meric’s model, Lee et al. have developed a compact model of extremely scaled graphene FETs.[38] In Lee’s model, an electron–hole puddle existing near the charge-neutral region (Dirac point) is considered at a low carrier density while the velocity saturation effect due to surface polar phonon scattering is included at a high carrier density. Frègonése et al.also proposed an electrical compact model for graphene FET device[39] at which, a trap model is introduced and the equivalent circuit is improved. And traps have an effect on the transconductance and influence consequently most figures of merit in circuit design. The electrical compact mode has been verified by comparison to DC and AC measurements versus bias and frequency on an advanced GFET having a transit frequency of about 10 GHz.

Although Meric’s model has firstly been developed and shown good agreement between experimental data and simulated results of drain current, due to the difference between MOSFET and GFETs, it maybe not entirely practicable to GFETs.

4. Compact model based on Boltzmann equation

To build a compact model accurately reflecting the characteristics of GFETs, researchers have presented the model based on Boltzmann equation.[46] Here, the graphene monolayer is assumed to sit on a thick SiO layer with capacitance on top of a back gate that controls the source and drain resistance , at the same time, as the channel threshold voltage with bias . A top gate of length L, separated from the graphene monolayer by a thinner oxide with capacitance , controls the carriers in the channel with . According to Boltzmann equation, by integrating the current of Eq. (11) from source to drain as in conventional MOS devices, and by taking into account the series resistance at the source and drain,[35] Scott et al. have obtained the drain current[46]

(33)
where
is the threshold voltage, here and , is the resistance. By solving for , a closed expression for the drain current is expressed as
(34)
where is the drain-source voltage,
and , is the critical field.

Here, the low drain-source bias conductance is readily calculated by taking the derivative of the current expression (Eq. (34)) with respect to as goes to zero. One obtains

(35)
where , so that is independent of , as is the conductance at low drain bias. The low drainsource bias resistance reads
(36)
which establishes a linear relation between and with a slope given by (inversely proportional to the mobility) and an asymptotic conductance value for large reaching .

In the same context, one obtains the expression for the drain-source saturation voltage as a function of the top gate voltage by solving for after setting the derivative of the current from Eq. (34) with respect to equal to zero that yields

(37)
with . Substituting Eq. (37) into Eq. (34), one can obtain the expression of the saturation drain current as a function of the top gate voltage, which reads
(38)
By taking the derivative of the saturation current with respect to the top gate voltage, one derives the expression for the transconductance at saturation
(39)
Figure 5 shows the plots of both the low-bias conductance as a function of the top gate voltage and the low-bias resistance as a function of the inverse of the top gate voltage in the device configuration investigated in Ref. [35]. In Fig. 5(a), the solid curve is calculated from Eq. (35), which shows good agreement with the experimental data close to the minimum conductance, but underestimates the former by about 20% at high top gate bias. In Fig. 5(b), the experimental resistance displays a linear relation with in agreement with Eq. (36).

Fig. 5. (a) Small-signal source-drain conductance as a function of the top gate voltage minus the threshold voltage , and (b) small-signal source-drain resistance as a function of the inverse of the top gate voltage minus the threshold voltage .[46]

Figure 6(a) displays the I–V characteristics of the GFET. An excellent agreement between the experiment and simulated results from Eq. (34) is obtained. However, the mobility is 25% higher than Meric’s fitted values.[35] Figure 6(b) shows the comparison between theoretical and experimental results for the p-channel conductance. The better fits are shown as compared with Meric’s results.[35] Besides the simulated drain current, Scott et al. in their compact model have predicted a linear dependence of the low-field resistance versus the inverse gate voltage, and suggested that nonlinearity in the energy dispersion should be included, as well as carrier multiplication by impact ionization.

Fig. 6. (a) Small-signal source-drain current as a function of drain-source voltage , and (b) small-signal source-drain conductance as a function of the top gate voltage minus the threshold voltage .[46]
5. Compact model based on drift-diffusion carrier transport

Based on drift-diffusion carrier transport, Jiménez et al. have presented a physics-based compact model of the current–voltage characteristics of GFET, of especial interest for analog and RF applications where band-gap engineering of graphene could not be needed.[41,42] They assumed that the electrostatics of this device is the equivalent capacitive circuit, in which the equivalent capacitive circuit and are the top and bottom oxide capacitances, and represents the quantum capacitance of the graphene. Potential represents the voltage drop across , where under condition , with , and is the Fermi velocity. Potential V(x) is the voltage drop in the graphene channel, which is zero at the source end at x = 0 and equal to drain-source voltage at the drain end at x = L. Then, to model the drain current, a drift-diffusion carrier transport is assumed under form

(40)
where W is the gate width, is the free carrier sheet density in the channel at position x, and v(x) is the carrier drift velocity. By using a soft-saturation model, consistent with Monte Carlo simulations,[70] v(x) can be expressed as
(41)
where E is the electric field, μ is the carrier low field mobility, and is the saturation velocity. The latter is concentration dependent and given by . By applying , combining the above expressions for v and , and integrating the resulting equation over the device length, the drain current becomes
(42)
The denominator represents an effective length ( ) to take into account the saturation velocity effect. In order to get an explicit expression for , the integral in Eq. (42) is solved by using as the integration variable and consistently expressing and as a function of ,
(43)
where can be written as
(44)

The positive (negative) sign applies whenever . The channel potential at source is determined by . Similarly, the channel potential at drain is determined by ). On the other hand, the charge sheet density can be written as . Extra term added to accounts for the carrier density induced by impurities.[71] By inserting these expressions into Eq. (42), the following explicit drain current expression can be finally obtained:

(45)
To test the model, Jiménez et al. have benchmarked the resulting I–V characteristics with experimental results extracted from devices in Refs. [35] and [72], as shown in Fig. 7. The first device under test has m and m, top dielectric is HfO of 15 nm, and permittivity is ∼ 16, and the bottom dielectric is silicon oxide of 285 nm. The back-gate voltage was −40 V. The flat-band voltages and were tuned to 1.45 V and 2.7 V, respectively. These values were selected to locate the Dirac point according to the experiment. Figure 8 shows the resulting I–V characteristics. Here the authors have extended the simulated voltage range beyond the experiment range to show the predictive behavior of the model. The transfer characteristics exhibit an ambipolar behavior dominated by holes (electrons) for where (Dirac gate voltage) is given by . The output characteristics are similar to those of the first examined device. Once again, the comparison between the model and experiment further demonstrates the accuracy of the model.

Fig. 7. (color online) Output characteristics obtained from the analytical model (solid lines) compared with experimental results (symbols) from Ref. [35]. Inset: quantum capacitance voltage drop as a function of the source-drain voltage for different gate voltage overdrive.[42]
Fig. 8. (color online) (a) Transfer and (b) output characteristics obtained from the compact model (solid lines) compared with experimental results (symbols) from Refs. [42] and [72].

Based on drift-diffusion carrier transport, Jiménez et al. have presented a physics-based compact model of current–voltage characteristics of GFETs, which can capture the physics of all operation regions within a single expression for the drain current and each terminal charge and capacitance. At the same time, it is of special interest as a tool for the design of analog and RF applications. Additional physical effects, for example, short-channel effects, nonquasi-static effects, extrinsic capacitances, and mobility model, need to be incorporated into the long-channel core presented here to build a complete GFET compact model.

6. Compact model based on density of states

To evaluate the capabilities of electronic devices based on graphene as a channel material, accurate models are desired. Some new compact models based on physics-based DOS have also been developed. For example, Aguirre–Morales et al. have developed a new compact model for monolayer graphene FETs and dual-gate bilayer GFET by using a physics-based DOS to simulate the current and the charge, respectively.[32,49–51]

6.1. Monolayer graphene FETs

For the monolayer graphene FETs, the model considering the 2D DOS of monolayer graphene is used as Eq. (16). The corresponding device and equivalent capacitive circuit of monolayer GFET are shown in Fig. 9.[49] As shown in Fig. 9(a), the graphene film is located between the top and the back-gate dielectrics. The source and drain ohmic contacts as well as the top-gate stack are located on the top of the graphene channel. The back-gate stack is comprised of a dielectric and a substrate acting as the back-gate. In this structure, the access region resistances are modeled as a function of the applied back-gate bias. The model is based on the 2D DOS of monolayer graphene being proportional to the Fermi level energy .

Fig. 9. (color online) (a) Cross section view and (b) equivalent capacitive circuit of monolayer GFET structure.[50]

For the monolayer GFETs, the drain current has also been derived from the general drift-diffusion equation and considered the velocity saturation of carriers[73] which reads

(46)
where is the stored charge density in the channel and accounts for the formation of hole and electron puddles in the graphene sheet[66] Δ represents the spatial inhomogeneity of the electrostatic potential and is the Fermi velocity. To account for this asymmetric conduction behavior, a separation of electron and hole branch contributions is necessary for the total drain current implementation, the total drain current can be written as the sum of the hole and electron contributions ( ) as
(47)
where ( , , ), and ( , , ) are the charge sheet density, saturation velocity, and mobility for electrons and holes respectively. The net stored charge density in the channel can be written as
(48)
Under the applied bias voltages ( , , ), one can write a second degree equation of the channel potential by solving the charge equations from the equivalent capacitive circuit shown in Fig. 9(b)
(49)
with , , and , where and are the top and back gate capacitances, respectively. is the net doping in the graphene channel. and are the intrinsic voltages within the structure v(x) is the voltage drop across the graphene channel. along the channel depends on the bias conditions of the graphene layer. Then, based on Eq. (49), the net charge due to electron and hole conductions leads to the following equations
(50)
Finally, the gate-source and gate-drain capacitances are calculated using the following equations:
(51)
with .

For verifying the model described above, measurement results from two different monolayer GFET technologies have been compared with the model simulations. Figure 10 shows the DC characteristics ( – , – , – ) from a device having a gate length of 5 μm and width of 25 μm.[36] The simulation shows a good agreement with the measured results.

Fig. 10. (color online) Comparison of (a) – , (b) – , (c) – , and (d) – measurements (symbols) with the compact model (solid lines).[50]
6.2. Bilayer graphene FETs

For the bilayer graphene FETs, the model considering DOS of bilayer graphene is used as Eq. (17). The corresponding device and equivalent capacitive circuit of bilayer GFET are shown in Fig. 11.[49] It is assumed that on top of the bilayer graphene channel, the source and drain ohmic contacts as well as the top-gate stack are located. The back-gate stack is composed of a dielectric and a substrate acting as the back-gate.

Fig. 11. (color online) (a) Cross-sectional view and the equivalent drain and source access resistances, and (b) equivalent capacitive circuit of bilayer GFET structure. Inset: DOS of bilayer graphene with a nonzero energy bandgap.[49]

The drain current in the bilayer graphene FETs can also be expressed as the sum of the electron and hole contributions, , which is similar to that in the monolayer graphene FETs.

The saturation velocity of carriers is given by

(52)
with being the effective energy due to phonon scattering in the substrate. Here, an even distribution of the residual carrier density in the electron and hole puddles is considered.

As the back-gate voltage becomes more negative, more positivecharges are induced to close the back-gate, thereby inducing more negative charges close to the graphene channel on the top side of the back-gate dielectric. Thus, higher values of are required to obtain the channel charge inversion, resulting in a shift in the Dirac point toward the positive direction. Then, the shift in the Dirac voltage will also saturate eventually as described by the exponential model

(53)
where , , and are constants.

Considering that the areas of hole and electron puddles are equal in size, the spatial electrostatic potential is simplified as a step function with a peak-to-peak value of , as presented in Ref. [66], which includes the effect of the opening of an energy bandgap. The electron and hole puddles are written as

(54)
In order to validate the capability of the developed compact model for accurate modeling of the bilayer GFET devices, comparisons with measurements from the literature[74] have been performed and are presented. The comparison of the measurement data and the developed compact model is shown in Fig. 12, which shows the good agreement.

Fig. 12. (color online) Comparison of the – measurements[34] (symbols) with the compact model (solid lines) for V and V to −60 V.[49]
7. Surface-potential-based compact model

As described above, plenty of compact models for GFETs have been developed with the current characteristics and can be implemented in Verilog-A for simulations of DC, AC, or transient properties. However, to achieve an accurate model qualified in EDA tool, the compact model with high accuracy and strong physical property should be further considered. For the real graphene device, the random distribution of carriers (electron or hole) caused by the impurities and spatial disorder will play a role in carrier transport. Thus, to obtain an accurate transport property, compact model in GFETs should include the real physical effect, such as disorder and temperature. The surface-potential-based compact model is believed to have high accuracy and strong physical property, and be easily simplified into the charge-based and threshold-voltage-based models.

Based on the surface-potential-based, Li et al. have developed a continuous physical compact model for GFET. Figure 13(a) shows the schematic diagram of a top-gated GFET for GEFT compact model.[47,48] In Li et al.’s work, it is assumed that on top of the graphene channel, the source and drain ohmic contacts as well as the top-gate stack are located. And DOS for graphene is Gaussian DOS with disorder parameter, and the analytical carrier density is based on the exponential distribution of potential fluctuations for the electron branch ( ) or the hole branch ( ).

Fig. 13. (color online) (a) Geometric definition for compact model of GFET, (b) capacitance divider scheme extracted from a single gated GFET, and (c) extrinsic structure for GFET.[48]
7.1. Surface-potential- based model

Generally, the threshold voltage emphasizes the converting point, while the surface potential always generates a continuous transition behavior covering the whole region. For the zero band-gap graphene, carriers generally degenerate with Fermi level located in the conduction or valence energy band. In this situation, the surface potential is obtained by using capacitance divider scheme instead of Poisson equation as shown in Fig. 13(b). For a single gate GFET, is expressed as

(55)
where sgn is the sign function, , v(x) is the voltage along the channel, V(0) or V(L) represents the source or drain voltage, is the gate doping voltage which will cause the drift of Dirac point. Equation (55) is applicable for high gate voltage region arising from the simple quantum capacitance. However, at the low gate voltage, the disorder effect dominates the transport and hence demands the accurate . With the Gaussian distribution of potential fluctuations,[75] although can achieve the high accuracy, it also blocks the analytical solution of . Fortunately, this question has been addressed by Li et al. by using the exponential distribution instead of Gaussian form.[76]

Based on Ref. [76], the surface potential can be obtained by solving the following equation:

(56)
where is the effective capacitance of the metal and graphene contact, , and is the effective contact distance. By using the Taylor series, the final surface potential can be written as
(57)

7.2. Asymmetry behaviors

It is well known that ambipolar characteristic curves in GFET show an asymmetry for electron and hole, which mainly derives from contact metal doping. Thus, the corresponding model should be modified. Based on the contact resistances as shown in Fig. 13(c), Li et al.developed the intrinsic voltage as[47,48]

(58)
where and are the intrinsic and extrinsic drain-source voltages, respectively, and is the drain-source current related to . Equation (58) can only be solved numerically with contact resistance for hole (electron). Considering the contribution of the contact doping to the surface potential, the asymmetry surface potential can be obtained by altering the effective contact capacitance in different operation regions. Then, the asymmetry surface potential is written as
(59)
where is a fitting parameter and its sign controls the type of metal doping, the detailed parameter is shown in Table 1.

Table 1.

Different metal-graphene contact and channel related to fitting parameter .

.

Based on Eq. (59), one can calculate the surface potential with numerical and analytical solutions, as shown in Fig. 14. The corresponding small error is shown in the inset.

Fig. 14. (color online) Simulation results of surface potential with numerical and analytical solutions, respectively. Inset: the error between numerical and analytical solutions.[47,48]
7.3. Current modeling

Generally, the constant mobility instead of function of Fermi level in model was applied. To achieve a higher level, the functional current will be simplified and then accuracy is reduced. To obtain carrier transport property, Li et al. introduced thermal activated transport theory and Bolzmann transport theory into the surface-potential-based model.[48] Electron or hole will contribute to the thermal activated transport[77] in the low Fermi level region, while in the high Fermi level, the Boltzmann transport will be dominant and include two scattering mechanisms (long-range and short-range). Based on these theories, the current should include three components as

(60)
where the subscripts d, long, and short represent the thermal activated, long-range scattering, and short-range scattering mechanisms, respectively, ( ) represents the drain (source) surface potential obtained by Eq. (57). Due to the competence of the two scattering mechanisms and the geometric mean presenting the transition from the thermal activation to Boltzmann transport, the final current model is expressed as
(61)
where and are the fitting parameters.

In Figs. 15(a) and 15(b), the comparison of the calculated and experimental results for output and transfer current characteristics is presented.

Fig. 15. (color online) (a) The output current under different gate voltages for the calculated and experimental results, and (b) transfer current under different drain voltages for the calculated and experimental results. Output current with simulated and experimental resutls under (c) nm and (d) nm.[47,48]

For current models, the output current saturation is always considered, which arises from drift velocity saturation or Joule heating effects. Generally, model with drift velocity saturation is written as the effective length expression

(62)
where is the saturation velocity. As well as typical models for and μ, various effective channel length expressions can be obtained. Actually equation (62) can be fully simplified with constant mobility and non-disorder carrier density . Then, equation (62) will be transformed as
(63)

According to Eq. (63), a model including residue carrier density ( ) or disorder parameter ( ) has been evolved. Remarkably, the effective length with the scattering mechanisms dependent mobility can be improved. embedded with two scattering mechanisms can be simply presented as

(64)
Based on Eq. (64), the comparison of saturation output current for the calculated and experimental results under different channel lengths is presented in Figs. 15(c) and 15(d).

7.4. Capacitance model

The terminal charges , , and always relate with the gate, drain, and source electrodes. is the integration of the net mobile carrier concentration along the channel. and can be obtained by Ward–Dutton’s linear charge partition scheme,[41,47] with the charge conservation relationship. The expressions for terminal charges are written as

(65)
Due to the current continuity equation, in Eq. (65) can be replaced by and y is equal to . Generally, if one considers the simple current model with constant mobility, disorder induced carrier density can be introduced into Eq. (63). Then, the capacitance model can be deduced analytically by using the formula
(66)
where i and j represent the terminals. As the gate oxide thickness is greatly decreased, the quantum capacitance needs to account for accurate intrinsic capacitance modeling during circuit simulation. Quantum capacitance induced by disorder is significant in discussing scaling down effect. The comparison of capacitance for the calculated and experimental results is shown in Fig. 16.

Fig. 16. (color online) Comparison of , , and . The lines represent the calculated results, and the points represent the experimental results.[47,48]
7.5. Parameter extraction

The computable effective and physics-based extraction method will benefit the compact model’s accuracy. Generally, extraction aims at being physical and fitting parameters. To obtain higher level, the parameter sequence should introduce physical effect. However, considering the continuity and accuracy of compact model, the fitting parameters will be used for smoothing the output curves and reducing the error. It is anticipated that the compact model of GFETs with the parameter sets will be suitable to circuit design and can provide accurate insight into the performance. The main criterion for a good set of parameters is the balance of error, efficiency, and continuity. Figure 17 shows the extraction flow of the key physical parameters of the surface-potential-based compact model.[47,48] Based on the corresponding equations shown in Fig. 17, four key parameters which determine the transport mechanisms can be obtained. Generally speaking, the self-consistent physics-based model is easier to extract the physical parameters. But, it is incompatible to propose a unified method of parameter extraction due to quite complicated models.

Fig. 17. (color online) Extraction flow of the key physical parameters of the model.[47]
7.6. Gummel symmetry test

For convergence in simulation and analysis for GFET based circuit, continuity and symmetry characteristics have to be kept. On the other hand, to simulate RF circuit, the corresponding parameters should satisfy the continuous and symmetry conditions. Compact model must fulfill one of the benchmark tests, that is, Gummel symmetry test (GST).[78,79] The traditional GST circuit is shown in Fig. 18. Generally, the higher-order derivatives in MOSFET compact models are obtained as a function of , which is symmetry for . This symmetry roots in the symmetry device structure and channel.

Fig. 18. Traditional GST circuit.

For GFETs, the symmetry is different from the transitional devices due to the drift of Dirac point. Depletion layer in the channel has disappeared in GFETs. In the capacitance divider scheme, this doping effect causes the asymmetry for plus and minus branches of drain voltage. Thus, to achieve GST, an applied gate-voltage will supplement the drift voltage. Otherwise, to control the continuity, the boundary conditions of the transition of different transport mechanisms cannot be ignored. To achieve it, the current components cover the whole region to avoid the sharp change at some typical points. For , the hole and electron branches will meet, where smoothing parameter in sgn function will be used for better continuity. If the model passes the GST, as shown in Fig. 19, one can claim that the model has a good continuity and symmetry.

Fig. 19. (color online) GST for 1, 2, 3-order derivatives of under the condition .[47,48]}
7.7. Simulation of GFET-based circuits

To embed the compact model into a vendor simulator, the Verilog-A hardware description language (HDL) language is always used for constructing a circuit level model. VA HDL is used for designing analog and mixed-signal systems and integrated circuits defined modules which encapsulate high-level behavioral descriptions as well structural descriptions. Here the surface-potential-based compact model is coded by using Verilog-A language.[80] The parameter declaration, surface-potential calculation, output current, and capacitance are shown in Fig. 20.

Fig. 20. (color online) Verilog-A module for compact model of GFET.
8. Conclusions and outlook

We have reviewed the concept, origin, development, and application of compact model within the scope of graphene field-effect transistors (GFETs). Although the compact model has a short history since it appeared, it seems that research interest in the compact model has been growing greatly. Based on the several current contributions, we have tried to describe plenty of methods on developing the GFET compact model. The merits and demerits for current compact model have also been discussed. To keep pace with the increase of circuit operating frequencies and device tolerances scale down with concomitant increases in chip device count, accurate and physics-based compact models are essential for the design and development of GFETs. Currently, the compact model is still open and evolvable. We hope that this review will be helpful to comprehensive understanding of GFETs compact model, and provide a motivation for promoting the application of GFETs in industry.

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